Search - Ethernet MAC

[WinSock-NDIS] 读取网卡mac

Description: 用VC++开发读取网卡MAC地址的程序，可以作为验证软件合法的一个通用模块 -with VC read the Ethernet MAC address procedures, the software can be verified as legitimate a Universal Module
Platform: | Size: 25923 | Author: 邵志民 | Hits:

[Windows Develop] MAC-modify

Description: 修改网卡MAC地址，比较方便-Ethernet MAC address changes, more convenient
Platform: | Size: 32768 | Author: | Hits:

[Internet-Network] 读取网卡mac

[matlab] mex

Description: matlab下面仿真802.3协议以太网mac层10、100M的网络接口模型。包括pci接口。-Matlab simulation 802.3 Ethernet mac agreement layer 10, 100M network interface model. Including PCI interface.
Platform: | Size: 24576 | Author: 仁刃 | Hits:

[VHDL-FPGA-Verilog] EthernetMAC10100Mbps.tar

Description: ethernet 10 0M MAC-ethernet MAC 10,100 M
Platform: | Size: 934912 | Author: wing | Hits:

[VHDL-FPGA-Verilog] MAC

Description: 10M/100M以太网mac子层802.3协议的源代码，包括半双工和全双工。-Mac sublayer 10M/100M Ethernet 802.3 protocol source code, including half-duplex and full duplex.
Platform: | Size: 122880 | Author: fiercewind | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[VHDL-FPGA-Verilog] ethernet

Description: 以太网控制器VHDL实现以及相关参考文档，超有使用价值，请仔细阅览-ethernet MAC controller VHDL realize
Platform: | Size: 1015808 | Author: yanglun | Hits:

[VHDL-FPGA-Verilog] MAC

Description: Verilog code for MAC
Platform: | Size: 1053696 | Author: dheeru | Hits:

[VHDL-FPGA-Verilog] ethernet_tri_mode.rel-1-0.tar

Description: ethernet mac verilog code.eth 10 100 1000mb/s
Platform: | Size: 690176 | Author: amir | Hits:

[VHDL-FPGA-Verilog] ethernet

Description: 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
Platform: | Size: 844800 | Author: wm | Hits:

[VHDL-FPGA-Verilog] EthernetUDP

Description: ethernet mac core.this is the etherenet udp application
Platform: | Size: 147456 | Author: suren | Hits:

[Other] ethernet_tri_mode_latest.tar

Description: 10_100 0 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.-10_100_1000 Mbps tri-mode ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependance.To increase the flexibility,three optional modules can be added to or removed from the project. A GUI configuration interface,created by tcl/tk script language,is convenient for configuring optional modules,FiFo depth and verifcation parameters. Furthermore,a verifcation system was designed with tcl/tk user interface,by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.
Platform: | Size: 3198976 | Author: Gopi | Hits:

[VHDL-FPGA-Verilog] ethmac_latest

Description: 以太网MAC，已经通过测试，详细说明见内README-Ethernet MAC, has been tested in more detail, see README
Platform: | Size: 933888 | Author: tz | Hits:

[Software Engineering] FPGAMAC

Description: 本文介绍了基于现场可编程门阵列(FPGA) 的以太网MAC 子层协议的硬件实现方法. 硬件结构上由控制模块、发送模块和接收模块3个部分组成,发送模块和接收模块采用状态机控制数据发送和接收的过程,完成数据的封装、发送和接收功能.-This article describes the field programmable gate array-based (FPGA) Ethernet MAC sub-layer protocol of the hardware implementation. Hardware architecture by the control module, sending module and receiver module three parts, sending module and receiver module using state machine control data sending and receiving process, the completion of the data package, send and receive functions.
Platform: | Size: 189440 | Author: 艾无止境 | Hits:

[VHDL-FPGA-Verilog] MAC_Transceiver

Description: MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。 -MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethernet data link layer part of the use of FPGA alternative ASIC, Ethernet MAC functionality is very useful. Hardware system to achieve multi-channel multi-port Ethernet access and Ethernet access to its own development needs of embedded processor design has been applied. To specifically explore the functional definition of the Ethernet MAC using FPGA Ethernet MAC method, the design of Ethernet-related applications guide.
Platform: | Size: 1572864 | Author: 陈辉 | Hits:

[source in ebook] verilog

Description: verilog描述的以太网MAC层源代码，功能正确，已经在FPGA开发板上测试！需要的赶紧下-verilog description of the Ethernet MAC layer source code, function correctly, has been tested in the FPGA development board! Need to hurry the next! ! !
Platform: | Size: 56320 | Author: WangYong | Hits:

[VHDL-FPGA-Verilog] ethernet_10G

Description: 10-Gigabit Ethernet MAC 内有说明文件方便阅读程序-10-Gigabit Ethernet MAC documentation within easy reader
Platform: | Size: 770048 | Author: lishufei | Hits:

[Embeded-SCM Develop] Virtex-5EMAC

Description: This application note describes a system using the Virtex™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri-Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.-This application note describes a system using the Virtex ™ -5 Embedded Tri-Mode Ethernet MAC (Ethernet MAC) Wrapper core on a Xilinx Virtex-5 ML505 development board. The system provides an example of how to integrate the Virtex-5 Embedded Tri- Mode Ethernet MAC and the Virtex-5 Embedded Tri-Mode Ethernet MAC wrapper using a hardware design to target the development board, and a PC-based Graphical User Interface (GUI) to control the demonstration platform.
Platform: | Size: 492544 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] Ethernet

Description: xilinx xupv5-110t ethernet mac调试，工程已做好，直接可用。-xilinx xupv5-110t ethernet mac
Platform: | Size: 4126720 | Author: 杨勇 | Hits:

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[WinSock-NDIS] 读取网卡mac

[Windows Develop] MAC-modify

[Internet-Network] 读取网卡mac

[matlab] mex

[VHDL-FPGA-Verilog] EthernetMAC10100Mbps.tar

[VHDL-FPGA-Verilog] MAC

[VHDL-FPGA-Verilog] ethernet.tar

[VHDL-FPGA-Verilog] ethernet

[VHDL-FPGA-Verilog] MAC

[VHDL-FPGA-Verilog] ethernet_tri_mode.rel-1-0.tar

[VHDL-FPGA-Verilog] ethernet

[VHDL-FPGA-Verilog] EthernetUDP

[Other] ethernet_tri_mode_latest.tar

[VHDL-FPGA-Verilog] ethmac_latest

[Software Engineering] FPGAMAC

[VHDL-FPGA-Verilog] MAC_Transceiver

[source in ebook] verilog

[VHDL-FPGA-Verilog] ethernet_10G

[Embeded-SCM Develop] Virtex-5EMAC

[VHDL-FPGA-Verilog] Ethernet

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